Apple Silicon (Metal)

The Metal backend is the primary development target for Tribunus Compute. It targets Apple Silicon GPUs (M1 through M4) via Metal 3, with optional offload to the Apple Neural Engine (ANE) for supported operations. All compiler passes, the numerical oracle, and the runtime pipelines are first developed and tested on this backend before being ported to other targets.

Type: Primary · Status: In progress · Key Library: Metal 3, ANE

Metal Shading Language kernels are generated directly from the compiler IR. The codegen pass handles tile sizing, memory barrier placement, and threadgroup layout automatically based on the target chip’s GPU core count, local memory size, and cache topology. FP16 and BF16 inference are fully supported, with FP32 used only for the oracle’s golden reference and for operations that require higher precision.

ANE offload is available for matrix multiplication and convolution operations that meet the neural engine’s shape constraints. The runtime automatically routes eligible operations to the ANE while keeping the rest of the graph on the GPU. This hybrid execution model maximizes throughput on Apple Silicon’s unified memory architecture.

The compiler pass for Metal lowers each PhaseIR operation to a Metal kernel using tile-size heuristics calibrated per GPU generation. The pass also generates indirect command buffers (ICMD) for the decode pipeline, enabling CPU-free kernel dispatch during autoregressive generation.