Tenstorrent

The Tenstorrent backend will support Tribunus Compute on Tenstorrent’s data center and edge accelerators. It targets TT-NN for high-level operator composition and TT-Metalium for direct hardware control of Tenstorrent’s systolic array architecture and on-chip SRAM fabric.

Type: Tertiary · Status: Planned · Key Library: TT-NN, TT-Metalium

Tenstorrent’s architecture differs from traditional GPUs in that it exposes a programmable data movement fabric alongside the compute array. The backend maps compiler IR tensor operations onto TT-NN operations where available, and generates custom TT-Metalium kernels for operations that require explicit data movement scheduling. The static compilation model is a natural fit for Tenstorrent’s deterministic execution model: kernel launch order, data layout, and SRAM bank allocation are all specified at compile time, matching Tribunus’s compile-time architecture directly.

The compiler pass for Tenstorrent lowers each PhaseIR operation to a TT-NN operation descriptor or a TT-Metalium kernel. The pass accounts for the architecture’s bfloat16-native compute paths and its hierarchical memory topology (SRAM per Tensix core, shared L1, DRAM). Tile sizes are chosen to fit within each Tensix core’s local SRAM budget.

Development of the Tenstorrent backend is planned following the completion of the CUDA and ROCm backends. The numerical oracle will be extended with Tenstorrent-specific test cases that account for the architecture’s reduced-precision modes and its data-movement scheduling constraints.