Intel (oneDNN)

The oneDNN backend will enable Tribunus Compute on Intel hardware, covering both Intel Xeon CPUs (with AMX matrix extensions) and Intel Arc / Data Center GPU Max series via the Level Zero API. oneDNN provides hardware-tuned primitives for convolution, matrix multiplication, and normalization — the primary path for compute-heavy operations.

Type: Secondary · Status: Planned · Key Library: oneDNN, Level Zero

On Xeon CPUs, the backend leverages AMX tile registers for INT8 and BF16 matrix operations. On Intel GPUs, the Level Zero driver stack provides direct device control for kernel dispatch and memory management. The compiler IR lowers to oneDNN primitive descriptors where possible, with custom fallback kernels for operations not covered by the oneDNN catalog (attention, fused activation functions).

Like all backends, the oneDNN path will be subject to numerical oracle verification. Intel hardware has its own numerical characteristics — fused-multiply-add semantics differ from IEEE 754 at the per-operation level, and some GPU SKUs use reduced-precision accumulation modes. The oracle’s test corpus will include Intel-specific edge cases to ensure admitted kernels produce correct results.

The compiler pass for oneDNN maps each PhaseIR operation to either a oneDNN primitive descriptor or a custom kernel path. For Xeon targets, the pass configures AMX tile dimensions based on the available tile register count; for GPU targets, it selects appropriate kernel launch parameters for the Level Zero command queue.