AMD (ROCm)

The ROCm backend will bring Tribunus Compute to AMD GPUs. It targets ROCm 6 with rocBLAS for GEMM operations and the Composable Kernel (CK) library for custom operator support. The initial target architecture is AMD CDNA 3 (MI300 series), with subsequent support for RDNA 3 consumer GPUs.

Type: Secondary · Status: Planned · Key Library: ROCm 6, rocBLAS

Planned features include static kernel compilation via the ROCm compiler stack, integration with the numerical oracle for accuracy verification on AMD hardware, and performance tuning for AMD’s matrix core units. The backend shares the PhaseIR compiler IR and the six-check admission pipeline with all other backends — any kernel that passes the oracle on one target can be re-lowered for AMD without re-verification of the numerical contract.

The compiler pass for ROCm lowers each PhaseIR operation to a HIP kernel, using rocBLAS for GEMM paths and Composable Kernel templates for attention and normalization. Hipify-based translation from the CUDA backend’s Triton-generated kernels is being evaluated as an acceleration path, but all admitted kernels must pass the oracle’s AMD-specific test corpus to account for differences in fused-multiply-add semantics and accumulation precision.

Development of the ROCm backend is sequenced after the CUDA backend’s primary targets stabilize.